1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming bipolar transistor devices and to an integrated circuit product that includes such a bipolar device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. So-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element used when manufacturing integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If the voltage applied to the gate electrode is less than the threshold voltage of the transistor device, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when voltage that is equal to or less than the threshold voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Field effect transistors can be either N-type (NFET) devices or P-type (PFET) devices that are made with different type doping materials. In general, N-type devices are turned “ON” and P-type devices are turned “OFF” when a logically high voltage is applied to the gate electrode of such devices. Conversely, N-type devices are turned “OFF” and P-type devices are turned “ON” when a logically low voltage is applied to the gate electrode of such devices. Integrated circuit products may be manufactured using both N-type and P-type devices that are formed on the same chip or substrate. This is generally referred to as CMOS (Complementary Metal Oxide Semiconductor) technology.
Another type of semiconductor device is a so-called bipolar junction transistor. A bipolar transistor is comprised of three doped regions and it has two PN junctions. More specifically, a bipolar transistor is comprised of a collector region, a base region positioned within the collector region and an emitter region positioned within the base region. In a bipolar transistor, current flows from the emitter region, through the base region to the collector region. In a bipolar device, there is no current flow in the device unless the base is turned “ON.” Bipolar devices come in two different arrangements: NPN devices and PNP devices, which refer to the type of dopant used for the collector region, base region and emitter region, respectively, with NPN bipolar transistors being more prevalent in modern integrated circuit products. Bipolar devices typically exhibit large drive currents and can operate with a high degree of noise immunity. However, circuits made with bipolar transistors tend to exhibit high power consumption and they have relatively poor packing density.
BiCMOS is a technology wherein bipolar devices and both N-type and P-type field effect transistors are formed on the same substrate in an effort to take advantage of desirable characteristics of such devices while attempting to limit the impact of the negative characteristics of such devices. For example, BiCMOS circuits can produce more drive current than can a comparably sized circuit made using only CMOS technology.
FIGS. 1A-1H depict one illustrative prior art integrated circuit product 10 comprised of both bipolar transistors and N- and P-type field effect transistors formed on a common substrate or chip, i.e., a product manufactured using BiCMOS technology. As shown in FIGS. 1A-1B, the common semiconductor substrate 12 comprises a region 12A, where an illustrative bipolar transistor device 14 will be formed, and a region 12B, where a plurality of standard N-type and P-type field effect transistor devices 15 will be formed. In such an application, the bipolar transistor devices 14 may be used as part of the read-write circuitry for a memory cell to reduce access time, while the standard N-type and P-type field effect transistor devices 15 may be used in manufacturing logic circuits, etc.
At the point of fabrication depicted in FIGS. 1A-1B, illustrative isolation regions 16 have been formed in the substrate regions 12A, 12B using known techniques. The isolation structures 16 in the substrate region 12B define active regions 18 where the standard N-type and P-type field effect transistor devices 15 will be formed. The isolation structures 16 in the substrate region 12A define regions where the emitter region 14E, the base region 14B and the collector region 14C of the bipolar device 14 will be formed. The doped areas that define these regions are depicted in dashed lines in FIG. 1A as such doped regions have not yet been formed in the substrate region 12A. In manufacturing the product 10, various doped regions or wells (not shown) will also be formed in the active regions 18 of the substrate region 12A. As is well known to those skilled in the art, appropriate patterned masking layers are used when forming the various doped regions in the substrate 12. The timing as to when the various doped regions are formed may vary depending upon the particular application. In general, to the extent possible, a device manufacturer will make all implants of the same type and dose, e.g., N-type dopants across the entire wafer using a single masking layer to save time and cost. Thus, in general, when an ion implantation process is performed to introduce N-type dopants into some of the active regions 18 in the region 12B, e.g., to form N-doped source/drain regions for N-type transistor devices 15, the masking layer used during this implant process will be formed such that the desired region of the bipolar transistor 14 that is to receive an N-type dopant, e.g., an N-doped emitter region 14E, will also be implanted with N-type dopant material at the same time.
FIGS. 1C-1D depict the product 10 at a later stage of fabrication wherein illustrative gate structures 20 have been formed above the active regions 18 in the region 12B of the substrate and gate structures 22 have been formed above the emitter region 14E of the bipolar device 14. Various doped regions may have been formed in the substrate regions 12A, 12B for various reasons, but such doped regions are not depicted in the attached drawings so as to not needlessly complicate the current discussion. The gate structures 20, 22 are intended to be representative in nature. However, in one illustrative embodiment, the gate structures 20, 22 may be so-called “dummy” gate structures that are used when the gate structures of the device 10 are made using a so-called “replacement gate” process. In general, the replacement gate process involves formation of a dummy gate structure, comprised of a sacrificial layer of gate insulation material, e.g., silicon dioxide, and a sacrificial gate electrode structure, e.g., polysilicon, that effectively serves as placeholder materials while other processing activities are performed on the device, e.g., while one or more ion implantation processes are performed to form source/drain regions and while an activation anneal process is performed to activate the implanted dopant materials. Eventually, the sacrificial gate electrode and sacrificial gate insulation layer are removed to thereby define a gate cavity where the replacement gate structure, i.e., the high-k gate insulation layer and one or more metal layers, is formed in the gate cavity.
The gate structures 22 are not needed above the emitter region 14E for purposes of operating the bipolar device 14, but they are typically formed above bipolar device 14 in an effort to achieve better uniformity when performing the planarization process that is performed when making transistor devices using a replacement gate technique. Typically, the critical dimension or width 20W of the gate structures 20 is less than the critical width 22W of the gate structures 22 formed above the emitter 14E.
FIGS. 1E-1F depict the product 10 at a point in fabrication wherein an emitter ion implantation process is performed as part to the process to define the doped region that will constitute the emitter region 14E. Note that, various doped regions may have been formed in the substrate regions 12A, 12B in the process flow for various reasons, e.g., halo implant regions, extension implant regions, the collector region 14C, the base region 14B, etc., but they are not depicted in the attached drawings so as to not needlessly complicate the current discussion. As depicted in FIG. 1E, the above-described ion implantation process results in the formation of spaced-apart doped regions 24 in the area where the emitter region 14E will be formed. The emitter ion implantation process is typically performed using a dopant dose of about 1e15-4e15 ions/cm2 and an energy level that falls within the range of about 10-30 keV. Of course, the type of dopant used to form the spaced-apart doped regions 24 depends upon whether the device 14 is an NPN device or a PNP device. Importantly, during the emitter ion implantation step, the gate structures 22 act as an implantation mask, thereby resulting in the spaced-apart doped regions 24.
FIGS. 1G-1H depict the product after a heating process, such as an activation anneal process, has been performed to activate at least the implanted dopant materials in the spaced-apart doped regions 24 and to repair damage to the substrate 12 due to the performance of one or more ion implantation processes. While this heating process causes the dopant materials in the spaced-apart doped regions 24 to migrate, as simplistically depicted in FIG. 1G, due to the initial spacing between the spaced-apart doped regions 24, after the heating process is completed, there are gaps or spaces 26 where dopant material is not present in sufficient quantity to serve its intended purpose. In some cases, there may be a complete absence of any of the dopant materials included in the doped region 24 in such spaces 26. The spaces 26 are due, at least in part, to the fact that the emitter implant process is preformed through the “mask layer” that is comprised of the dummy gate structures 22. The formation of such spaces 26 in the emitter region 14E effectively results in a decrease of the size/effectiveness of the area of the emitter region 14E. As a result, the emitter region 14E must be sized larger than is necessary to account for the creation of the non-effective spaces 26 in the emitter region 14E that are present when forming the product using this illustrative prior art technique. Such an increase in the physical size of the emitter region 14E is highly undesirable as it will increase the overall physical size of the resulting chip, which is directly contrary to the constant demand to reduce the overall size and weight of integrated circuit products.
The present disclosure is directed to various methods of forming bipolar transistor devices and to an integrated circuit product that includes such a bipolar device that may solve or reduce one or more of the problems identified above.